Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the device size decreases.
In some integrated circuit designs there has been a desire to eliminate the use of polysilicon gate electrodes to improve device performance with decreased feature sizes. Replacing polysilicon gate structures with metal gate stacks is one solution. A typical metal gate stack includes a metal gate that overlies a high dielectric constant (high-K) dielectric layer on a semiconductor substrate. One approach to forming metal gate stacks employs a process known as replacement gate or replacement metal gate (RMG). The replacement gate process forms a dummy gate structure that is used to self-align source and drain implants and anneals in a semiconductor substrate. The dummy gate structure is then removed and replaced with the high-K and metal gate materials.
Additionally, it is known that the introduction of strain in semiconductor devices can enhance carrier mobility and therefore enhance drive current capabilities of such devices. For example, and not intending to be limiting, with a PFET, it is known that the use of source and drain regions formed of silicon-germanium (SiGe) alloy can provide compressive strain in the channel region located between the source and drain regions of the MOS device. This strain can increase carrier mobility in the channel region and significantly improve overall device properties. However, some practical difficulties may be encountered in implementing such structures particularly when using a replacement gate process to form the MOS device. For example, and not intending to be limiting, various cleaning and/or etching steps during the replacement gate process can result in the strain-inducing source and drain regions being too close to the metal gate edges, which can result in shorting or loss between the strain-inducing source and drain regions and the metal gate.
Accordingly, it is desirable to provide integrated circuits and methods of forming integrated circuits with improved replacement gate structures. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.